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1 ? fn9124.8 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 improved industry standard single-ended current mode pwm controller the isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 family of adjustable frequency, low power, pulse width modulating (pwm) current mode controllers is designed for a wide range of power conversion applications including boost, flyback, and isolated output configurations. peak current mode control effectively handles power transients and provides inherent overcurrent protection. this advanced bicmos design is pin compatible with the industry standard 384x family of controllers and offers significantly improved perfor mance. features include low operating current, 60 a start-up current, adjustable operating frequency to 2mhz, and high peak current drive capability with 20ns rise and fall times. features ? 1a mosfet gate driver ?60 a startup current, 100 a maximum ? 25ns propagation delay current sense to output ? fast transient response wit h peak current mode control ? adjustable switching frequency to 2mhz ? 20ns rise and fall times with 1nf output load ? trimmed timing capacitor disc harge current for accurate deadtime/maximum duty cycle control ? high bandwidth error amplifier ? tight tolerance voltage reference over line, load, and temperature ? tight tolerance current limit threshold ? pb-free plus anneal available (rohs compliant) applications ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems ? pc power supplies ? isolated buck and flyback regulators ? boost regulators pinout isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 8 ld soic, msop top view 8 ld dfn top view part number rising uvlo max. duty cycle isl6840 7.0 100% isl6841 7.0 50% isl6842 14.4v 100% isl6843 8.4v 100% isl6844 14.4v 50% ISL6845 8.4v 50% comp fb rtct vref vdd out gnd 1 2 3 4 8 cs 7 6 5 2 3 4 1 7 6 5 8 comp fb cs rtct vref vdd out gnd data sheet april 16, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2005, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9124.8 april 16, 2007 ordering information part number part marking temp. range (c) package pkg. dwg. # isl6840ib* isl 6840ib -40 to +105 8 ld soic m8.15 isl6840ibz* (see note) 6840 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6840iu* 6840 -40 to +105 8 ld msop m8.118 isl6840iuz* (see note) 6840z -40 to +105 8 ld msop (pb-free) m8.118 isl6841ib* isl 6841ib -40 to +105 8 ld soic m8.15 isl6841ibz* (see note) 6841 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6841iu* 6841 -40 to +105 8 ld msop m8.118 isl6841iuz* (see note) 6841z -40 to +105 8 ld msop (pb-free) m8.118 isl6842ib* isl 6842ib -40 to +105 8 ld soic m8.15 isl6842ibz* (see note) 6842 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6842iu* 6842 -40 to +105 8 ld msop m8.118 isl6842iuz* (see note) 6842z -40 to +105 8 ld msop (pb-free) m8.118 isl6843ib* isl 6843ib -40 to +105 8 ld soic m8.15 isl6843ibz* (see note) 6843 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6843iu* 6843 -40 to +105 8 ld msop m8.118 isl6843iuz* (see note) 6843z -40 to +105 8 ld msop (pb-free) m8.118 isl6844ib* isl 6844ib -40 to +105 8 ld soic m8.15 isl6844ibz* (see note) 6844 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6844iu* 6844 -40 to +105 8 ld msop m8.118 isl6844iuz (see note) 6844z -40 to +105 8 ld msop (pb-free) m8.118 ISL6845ib* isl 6845ib -40 to +105 8 ld soic m8.15 ISL6845ibz* (see note) 6845 ibz -40 to +105 8 ld soic (pb-free) m8.15 ISL6845iu* 6845 -40 to +105 8 ld msop m8.118 ISL6845iuz* (see note) 6845z -40 to +105 8 ld msop (pb-free) m8.118 isl6840irz-t? (see note) 40z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6841irz-t? (see note) 41z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6842irz-t (see note) 42z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6843irz-t (see note) 43z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6844irz-t? (see note) 44z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 ISL6845irz-t (see note) 45z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 *add -t to part number for tape and reel packaging. ?contact factory for availability note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds /die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking temp. range (c) package pkg. dwg. # isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
3 fn9124.8 april 16, 2007 functional block diagram on vdd cs fb rtct gnd pwm comparator reset dominant 2.5 v enable 8.4ma 2.6v 0.7v oscillator comparator + - uvlo comparator v ref 5.00 v + - bg + - 100mv error amplifier + - vref + - on + - s r q q comp vref uv comparator 4.65v 4.80v bg + - a = 0.5 + - clock 1.1v clamp 2r r t q q isl6841/4/5 only p/n uvlo on/off -40, -41 7.0/6.6v -42, -44 14.3/8.8v -43, -45 8.4/7.2v a vref fault v dd ok vref out isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
4 fn9124.8 april 16, 2007 typical application - 48v input dual output flyback vin+ vin- return t1 q3 36v to 75v vr1 +1.8v +3.3v c1 c2 c3 r1 r3 c4 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 c12 c11 r13 c8 r10 r6 cr1 + + c21 c19 c22 c20 + + c6 isl684x v dd rtct cs fb out comp vref gnd r26 r27 u4 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
5 fn9124.8 april 16, 2007 typical application - boost converter vin+ vin- c1 q1 r1 r4 cr1 c9 c8 r7 c2 c5 c6 c7 r3 + r2 c4 l1 c3 vin+ u1 isl684x out cs rtct fb comp vref vdd gnd +vout return r5 r6 r8 c10 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
6 fn9124.8 april 16, 2007 absolute maximum rati ngs thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a esd classification human body model (per mil-std-883 method 3015.7) . . .2000v charged device model (per eos/esd ds5.3, 4/14/93) . . .1000v operating conditions temperature range isl684xix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical, note 3) isl6840, isl6841. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5v to 14v isl6843, ISL6845. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 16v isl6842, isl6844. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v to 18v thermal resistance (typical, note 1, ) ja (c/w) jc (c/w) dfn package (note 2). . . . . . . . . . . . . 77 6 soic package . . . . . . . . . . . . . . . . . . . 100 n/a msop package . . . . . . . . . . . . . . . . . . 130 n/a maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (soic- lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150c max junction temperature is intended for short periods of time to prevent shortening the lifetime. constantly operated a t +150c may shorten the life of the part. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. all voltages are with respect to gnd. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. v dd = 15v (note 7), rt = 10k , ct = 3.3nf, t a = -40 to +105c (note 4), typical values are at t a = +25c parameter test conditions min typ max units undervoltage lockout start threshold (isl6840, isl6841) 6.5 7.0 7.5 v start threshold (isl6843, ISL6845) 7.8 8.4 9.0 v start threshold (isl6842, isl6844) 13.3 14.3 15.3 v stop threshold (isl6840, isl6841) 6.1 6.6 6.9 v stop threshold (isl6843, ISL6845) 6.7 7.2 7.7 v stop threshold (isl6842, isl6844) 8.0 8.8 9.6 v hysteresis (isl6840, isl6841) - 0.4 - v hysteresis (isl6843, ISL6845) - 0.8 - v hysteresis (isl6842, isl6844) - 5.4 - v startup current, i dd v dd < start threshold - 60 100 a operating current, i dd (note 5) - 3.3 4.0 ma operating supply current, i d includes 1nf gate loading - 4.1 5.5 ma reference voltage overall accuracy over line (v dd = 12v to 18v), load, temperature 4.925 5.000 5.050 v long term stability t a = +125c, 1000 hours (note 6) - 5 - mv fault voltage 4.40 4.65 4.85 v vref good voltage 4.60 4.80 vref - 0.05 v hysteresis 50 165 250 mv current limit, sourcing -20 - - ma current limit, sinking 5 - - ma isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
7 fn9124.8 april 16, 2007 current sense input bias current v cs = 1v -1.0 - 1.0 a cs offset voltage v cs = 0v (note 6) 95 100 105 mv comp to pwm comparator offset voltage v cs = 0v (note 6) 0.80 1.15 1.30 v input signal, maximum 0.91 0.97 1.03 v gain, a cs = v comp / v cs 0 < v cs < 910mv, v fb = 0v (note 6) 2.5 3.0 3.5 v/v cs to out delay (note 6) - 25 40 ns error amplifier open loop voltage gain (note 6) 60 90 - db unity gain bandwidth (note 6) 3.5 5 - mhz reference voltage v fb = v comp 2.475 2.514 2.55 v fb input bias current v fb = 0v -1.0 -0.2 1.0 a comp sink current v comp = 1.5v, v fb = 2.7v 1.0 - - ma comp source current v comp = 1.5v, v fb = 2.3v -0.4 - - ma comp voh v fb = 2.3v 4.80 - vref v comp vol v fb = 2.7v 0.4 - 1.0 v psrr frequency = 120hz, v dd = 12v to 18v (note 6) 60 80 - db oscillator frequency accuracy initial, t j = +25c 49 52 55 khz frequency variation with v dd t = +25c (f 18v - f 12v )/f 12v -0.21.0% temperature stability (note 6) - - 5 % amplitude, peak to peak - 1.9 - v rtct discharge voltage - 0.7 - v discharge current rtct = 2.0v 7.2 8.4 9.5 ma output gate voh v dd to out, i out = -200ma - 1.0 2.0 v gate vol out tognd, i out = 200ma - 1.0 2.0 v peak output current c out = 1nf (note 6) - 1.0 - a rise time c out = 1nf (note 6) - 20 40 ns fall time c out = 1nf (note 6) - 20 40 ns pwm maximum duty cycle isl6840, isl6842, isl6843 94 96 - % isl6841, isl6844, ISL6845 47 48 - % minimum duty cycle isl6840, isl6842, isl6843 - - 0 % isl6841, isl6844, ISL6845 - - 0 % notes: 4. specifications at -40c although guaranteed, are not 100% tested in production. 5. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 6. these parameters, although guaranteed, are not 100% tested in production. 7. adjust v dd above the start threshold and then lower to 15v. electrical specifications recommended operating conditions unles s otherwise noted. refer to block diagram and typical application schematic on page 3 and page 4. v dd = 15v (note 7), rt = 10k , ct = 3.3nf, t a = -40 to +105c (note 4), typical values are at t a = +25c (continued) parameter test conditions min typ max units isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
8 fn9124.8 april 16, 2007 pin descriptions rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, rt, between vref and this pin and a timing capacitor, ct, from this pin to gnd. the oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f, and the maximum duty cycle, dmax, can be calculated from equations 1, 2, 3 and 4: figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is connected between the comp and fb pins. fb - the output voltage feedback is connected to the inverting input of the error amplifier through this pin. the non-inverting input of the error amplifier is internally tied to a reference voltage. cs - this is the current sense input to the pwm comparator. the range of the input signal is nominally 0v to 1.0v and has an internal offset of 100mv. gnd - gnd is the power and small signal reference ground for all functions. out - this is the drive output to the power switching device. it is a high current output capable of driving the gate of a power mosfet with peak currents of 1.0a . this gate output is actively held low when v dd is below the uvlo threshold. vdd - v dd is the power connection for the device. the total supply current will depend on the load applied to out. total i dd current is the sum of th e operating current and the typical performance curves figure 1. frequency vs temperature fig ure 2. reference voltage vs temperature figure 3. ea reference vs temperature figure 4. resistance for ct capacitor values given 1.02 1.01 1.00 0.99 0.98 0.97 -40 -10 20 50 80 110 temperature (c) normalized frequency temperature (c) normalized v ref 1.001 1.000 0.999 0.998 0.997 0.996 0.995 -40 -25 -10 5 20 35 50 65 80 95 110 temperature (c) normalized ea reference 1.002 1.000 0.998 0.996 0.994 -40 -25 -10 5 20 35 50 65 80 95 110 10 3 100 10 1 10 20 30 40 50 60 70 80 90 100 rt (k ) frequency (hz) 100pf 220pf 330pf 470pf 1.0nf 2.2nf 3.3nf 4.7nf t c 0.583 rt ct ? ? (eq. 1) t d rt ? ct 0.0083 rt 4.3 ? ? 0.0083 rt 2.4 ? ? ---------------------------------------------- ?? ?? ln ? ? (eq. 2) f 1t c t d + () ? = (eq. 3) dt c f ? = (eq. 4) isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
9 fn9124.8 april 16, 2007 average output current. knowing the operating frequency, f, and the mosfet gate charge, qg, the average output current can be calculated in equation 5: to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. vref - the 5.00v reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. bypass to gnd with a 0.1 f to 3.3 f capacitor to filter this output as needed. functional description features the isl684x current mode pwms make an ideal choice for low-cost flyback and forward topology applications. with its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. oscillator the isl684x controllers have a sawtooth oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor from vref and a capacitor to gnd on the rtct pin. (please refer to figure 4 for the resistor and capacitance required for a given frequency.) soft-start operation soft-start must be implemented externally. one method, illustrated below, clamps the voltage on comp. gate drive the isl684x are capable of sourcing and sinking 1a peak current. to limit the peak current through the ic, an optional external resistor may be placed between the totem-pole output of the ic (out pin) and the gate of the mosfet. this small series resistor also da mps any oscillations caused by the resonant tank of the parasiti c inductances in the traces of the board and the fet?s input capacitance. slope compensation for applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. the minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. adding excessive slope compensation, however, results in a control loop that behaves more as a voltage mode controller than as current mode controller. slope compensation may added to the cs signal in the following manner. fault conditions a fault condition occurs if vref falls below 4.65v. when a fault is detected out is disabled. when vref exceeds 4.80v, the fault condition clears, and out is enabled. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. v dd should be bypassed directly to gnd with good high frequency capacitors. (eq. 5) i out qg f = figure 5. soft-start vref comp gnd isl684x time cs signal (v) downslope current sense signal figure 6. current sense downslope figure 7. slope compensation vref rtct cs isl684x isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845
10 fn9124.8 april 16, 2007 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
11 fn9124.8 april 16, 2007 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 0 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9124.8 april 16, 2007 isl6840, isl6841, isl6842, isl6843, isl6844, ISL6845 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3 8 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n82 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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